Presenting the Design of Low-Power High-Speed Two-Level Three input XOR Gate | Science and Technology: Developments and Applications Vol. 5

Author(s) Details:

Chaitanya Kommu
Department of EEC, GITAM University, Visakhapatnam, AP, India.

A Daisy Rani
Department of Instrument Technology, Andhra University, Visakhapatnam, AP, India.

 

This Section is a Part of the Chapter: Presenting the Design of Low-Power High-Speed Two-Level Three input XOR Gate

The Large Fan-In and high-performance gates are essential to make portable electronic devices. The efficient realization of high Fan-in XOR gate defines the performance of digital circuits like adders, magnitude comparators etc. In this paper, an efficient realization of three input two-level XOR(Exclusive-OR) is presented.

How to Cite

Kommu, C., & Rani, A. D. (2025). Presenting the Design of Low-Power High-Speed Two-Level Three input XOR Gate. Science and Technology: Developments and Applications Vol. 5, 1–14. https://doi.org/10.9734/bpi/stda/v5/2365

To Read the Complete Chapter See Here