Author(s) Details:
Chaitanya Kommu
Department of EEC, GITAM University, Visakhapatnam, AP, India.
A Daisy Rani
Department of Instrument Technology, Andhra University, Visakhapatnam, AP, India.
This section is a part of the chapter: Presenting the Design of Low-Power High-Speed Two-Level Three input XOR Gate
It is observed that inputs are not only applied at the gate terminal of MOSFET but also at the source/drain terminals of transistors therefore it is also called gate no-restored logic implementation. There is a serious problem inherent to the pass-gate logic is that it suffers from threshold problems (Kommu and Rani (2020), Kommu and Rani (2020). For example, let us consider the nMOS transistor and apply logic high at the gate terminal as well as the source/drain terminal it is observed that only (VDD-Vth) is the output signal strength after that the nMOS enters into the cutoff region.
How to Cite
Kommu, C., & Rani, A. D. (2025). Presenting the Design of Low-Power High-Speed Two-Level Three input XOR Gate. Science and Technology: Developments and Applications Vol. 5, 1–14. https://doi.org/10.9734/bpi/stda/v5/2365